1. Field of the Invention
The invention relates generally to a NAND-type memory array and method of reading, programming and erasing the same, and more particularly to, a NAND-type memory array and method of reading, programming and erasing the same capable of preventing lowering in the read speed by separating well and bit line.
2. Description of the Prior Art
Generally, in a NAND-type memory array using a deep trench isolation (DTI) scheme, all the well bias is applied via bit line upon reading, programming and erasure since it employs an independent well.
FIGS. 1A and 1B are cross-sectional views of a conventional NAND-type memory array, wherein FIG. 1A is a cross-sectional view of the memory array taken along in a word line direction of the array and FIG. 1B is a cross-sectional view of the memory array taken along in a bit line direction of the array.
A construction of the conventional NAND-type memory array will be described by reference to FIGS. 1A and 1B.
Referring now to FIG. 1A, a triple N well 12 is formed on a P type substrate 11 and triple P well 13 are then formed to be included in the triple N well 12. The triple P well 13 are divided by a plurality of numbers, by means of a plurality of dip trench device isolation films 14. Floating gates 17 are formed on the triple P well 13, respectively. Word lines 20 are overlapped with the floating gates 17.
Referring now to FIG. 1B, firstxcx9celeventh N+ junctions 15axcx9c15k and a P+ junction 16 are formed within the triple P well 13 in an isolated fashion. Firstxcx9csixth floating gates 17axcx9c17f are formed on the triple P well 13 in an isolated fashion. Source nodes 19 are connected to the second N+ junction 15b. Each of firstxcx9csecond source select lines 18a and 18b is formed at both sides of the second N+ junction 15b. A bit line 23 is connected to a P+ junction 16, and seventh and eighth N+ junctions 15g and 15h formed at both sides of the P+ junction 16, respectively.
A first drain select line 22a is formed at one side of the seventh N+ junction 15g and a second drain select line 22b is formed at one side of the eighth N+ junction 15h. Between a second source select line 18b and the first drain select line 22a, a first pass gate 20a is overlapped with the first floating gate 17a, a first cell gate 21a is overlapped with the second floating gate 17b, a second pass gate 20b is overlapped with the third floating gate 17c. At this time, the first cell gate 21b is located between the first pass gate 20a and the second pass gate 20b. Similarly in the second drain select line 22b, a third pass gate 20c is overlapped with the fourth floating gate 17d, a second cell gate 21b is overlapped with the fifth floating gate 17e and a fourth pass gate 20d is overlapped with the sixth floating gate 17f. 
In the above, each of the source node 19, the source select lines 18a and 18b, the drain select lines 22a and 22b, the pass gates 20axcx9c20d, and the cell gates 21a and 21b is formed in the triple P well 13 in a crossing direction. The bit line 23 is formed in a direction of the triple P well 13.
It is known that the NAND-type memory array is based on the above construction and this basic construction is constantly arranged.
An operation of reading, programming and erasing the conventional NAND-type memory array will be described by reference to FIG. 2 showing a node bias condition of the NAND-type memory array.
First, the read operation includes applying a voltage of 0xcx9c1V to the bit line 23, applying a voltage of 0V to the triple P well 13, applying a voltage of 3V to the source node 19, applying a voltage of 5V to the drain select line 22, applying a voltage of 5V to the source select line 18, applying a voltage of 3V to the cell gate 21 and applying a voltage of 3V to the triple N well 12.
The program operation includes applying a voltage of xe2x88x929V to the bit line 23, applying a voltage of xe2x88x929V to the triple P well 13, applying a voltage of 0V to the source node 19, applying a voltage of 0V to the drain select line 22, applying a voltage of xe2x88x929V to the source select line 18, applying a voltage of 9V to the cell gate 21 and applying a voltage of 0V to the triple N well 12.
The erase operation includes applying a voltage of 9V to the bit line 23, applying a voltage of 9V to the triple P well 13, making the source node 19 floated, making the drain select lines 22 floated, making the source select lines 18 floated, applying a voltage of xe2x88x929V the cell gate 21 and applying a voltage of 9V to the triple N well 12.
In the above conventional NAND-type memory array, as the triple P well 13 is independently driven by the dip trench device isolation film 14 in structure, it is required that all the well bias be applied via the bit line 23 upon reading, programming and erasure operation.
It is inevitable that the bias is applied to the well in programming and erasure operations using this method. In a reading operation, however, there is a problem that the read speed is lowered due to a well loading if this method is used. In other words, if a voltage of 3V is applied to the source node 19 and a voltage of 3V is applied to the cell gate 21 upon a reading operation, a bias passing the cell is applied to the bit line 23, which charges the well via the P+ junction 16. As such, as the loading of the triple P well 13 is generated upon a reading operation, delay in the speed is caused.
The present invention is contrived to solve this problem and an object of the present invention is to provide a NAND-type memory array and method of reading, programming and erasing the same capable of preventing lowering in the speed upon a reading operation, by separating well and bit line.
In order to accomplish the above object, a NAND-type memory array according to the present invention is characterized in that it comprises P type substrate in which a triple P well is formed; firstxcx9ceighth N+ junctions, a P+ junction and ninth fourteenth N+ junctions, which are sequentially formed within the triple P well; firstxcx9csixth floating gates formed on the triple P well; source node connected to the second N+ junction; first and second source select lines each formed at both sides of the second N+ junction; bit line each connected to the seventh and eleventh N+ junctions; first drain select line formed at one side of the N+ junction and second drain select line formed at one side of the eleventh N+ junction; first pass gate, first cell gate and second pass gate each formed between the second source select line and the first drain select line; third pass gate, second cell gate and fourth pass gate each formed on the triple P well on the second drain select linexe2x80x99 side; interconnection line connecting the eighth N+ junction, the P+ junction and the ninth N+ junction, respectively; program well select gate formed between the seventh N+ junction and the eighth N+ junction; P well node connected to the tenth N+ junction between the ninth N+ junction and the eleventh N+ junction; and triple P well select gate formed between the ninth N+ junction and the tenth N+ junction, wherein the elements being a basic construction and this basic construction is constantly arranged.
In the above, the triple P well is formed within the triple N well. The pass gates and the cell gates are overlapped with the floating gates, respectively. The cell gates have the pass gates located at its both side, respectively.
The source nodes, the source select lines, the drain select lines, the pass gates and the cell gates are each formed in a direction crossing with the triple P well. The bit line are formed in a direction of the triple P well.
A reading method in a NAND-type memory array comprises applying a voltage of 0xcx9c1V to a bit line, applying a voltage of 0xcx9c1V to a triple P well, applying a voltage of 3V to a source node, applying a voltage of 5V to a drain select line, applying a voltage of 5V to a source select line, applying a voltage of 0V to a program well select gate and applying a voltage of 3V to a triple P well select gate.
A programming method in a NAND-type memory array comprises applying a voltage of xe2x88x929V to a bit line, applying a voltage of 0V to a P well node, applying a voltage of 0V to a source node, applying a voltage of 0V to a drain select line, applying a voltage of 0V to a source select line, applying a voltage of 3V to a program well select gate and applying a voltage of xe2x88x929V to a triple P well select gate.
An erasing method in a NAND-type memory array comprises applying a voltage of 9V to a bit line, applying a voltage of 9V to a P well node, making a source node floated, making a drain select line floated, making a source select line floated, applying a voltage of 0V to a program well select gate and applying a voltage of 12V to a triple P well select gate.